cystech electronics corp. spec. no. : c552n5 issued date : 2010.10.26 revised date : page no. : 1/10 LM1101N5 cystek product specification 300ma high psrr low noise ldo LM1101N5 general description the LM1101N5 performs ultra low drop voltage, high power supply rejection ratio (psrr), fast response, low noise linear regulator, and designed to cont inuously deliver up to 300ma output current. the LM1101N5 has wide adjustable output voltage range and high output accuracy to 1.5%. no by-pass capacitor is needed for this device and only 1 f ceramic capacitor is required for stability in any loading conditions. it reduces the amount of board space necessary for power applications. the other features include soft start, current limit protection, power-on-reset function, and over temperature protection. the LM1101N5 is available in sot-23-5 package. features ultra fast response in line/load tr ansient ultra low output noise voltage 100 v (rms) wide v in range from 2.5v to 5.5v low shutdown current < 1 a adjustable output voltage from 0.8v to 4.5v only 1 f ceramic capacitor required for stability ultra low dropout voltage: 200mv @300ma over temperature protection high power supply rejection ratio current limit protection 70db at 1khz rohs compliant and 100% lead (pb)-free 60db at 10khz applications cellular handsets hand-held instruments battery-powered equipment pcmcia cards laptop, palmtops, notebook computers portable information applications ordering information part number package shipping LM1101N5 sot-23-5l (rohs compliant package) 3000 pcs / tape & reel pin configuration
cystech electronics corp. spec. no. : c552n5 issued date : 2010.10.26 revised date : page no. : 2/10 LM1101N5 cystek product specification typical application circuit pin name pin no. pin function en 1 chip enable input (active high). gnd 2 ground. vin 3 input voltage . this is the source input to the power device that supplies current to the output pin. vout 4 output voltage . v out is power output pin. an internal pull low resistance exists when the device is disabled. minimum 1 f low esr ceramic capacitor is required at this pin for stabilizing v out voltage. fb 5 feedback voltage . fb is the non-inverting input to the error amplifier. a resistor divider from the output to gnd is used to set the regulation voltage as v out ? = 0.8 * (1 ??+r 1 /r 2 )( ? v) . this pin has high impedance and should be kept from non-inverting input to noisy source to guarantee stable operation. pin assignment function block diagram
cystech electronics corp. spec. no. : c552n5 issued date : 2010.10.26 revised date : page no. : 3/10 LM1101N5 cystek product specification absolute maximum ratings (note 1) v in ---------------- ------------------ ---------------------------------- ------------------ -------- -0.3v to +6.0v other pins----------------- ------------------ ----------------- ------------------ ---------- -0.3v to (v in +0.3v) power dissipation, p d @ t a = 25 c, sot23-5 (note 2) ----------------- --------------- ------------ 0.4w package thermal resistance, ja , sot23-5 (note 2) -------------- --------------- -------------- 250 c/w package thermal resistance, jc , sot23-5 (note 2) -------------- --------------- ---------------- 25 c/w junction temperature----- ------------------------------------------------------------ --------------- 150 c lead temperature (soldering, 10 sec.)------------ ------------------------------ ------------------ 260 c storage temperature ------------ --------------- -------------------------------------------- -65 c to 150 c esd susceptibility (note3) hbm (human body mode)-------------- ---------------------------------- ------------------ ------- 2kv mm (machine mode)----- ---------------------------------- ------------------------------ ------------ 200v recommended operating conditions (note4) supply input voltage, v in ------------------ --------------------------------- ----------------- +2.5v to +5.5v junction temperature -------- ------------------------------------------------ ------------- ?-- 40 c to 125 c ambient temperature ------ ----------------- --------------------------------------------- ----- ? 40 c to 85 c electrical characteristics @ v in =5v, t a =25 , unless otherwise specified parameter symbol test conditions min typ max units supply input section power input voltage v in v out = v ref 2.5 - 5.5 v por threshold v porth - 2.0 2.4 v por hysteresis v porhys - 0.1 - v quiescent current i q v in =v en =5v, i out =0a - 90 130 a shutdown current i sd v in =5v,v en =0v - 0.1 1 a output voltage output voltage accuracy v out v in =v en =5v, i out =1ma -1.5 - 1.5 % line regulation v out(line) 2.5v cystech electronics corp. spec. no. : c552n5 issued date : 2010.10.26 revised date : page no. : 4/10 LM1101N5 cystek product specification parameter symbol test conditions min typ max units over current protection ocp threshold level i ocp v in =v en =5v, v out =v ref 360 600 - ma thermal protection thermal shutdown temperature t sd v in =v en =5v, i out =0a, v out =v ref - 160 - c thermal shutdown hysteresis t sdhys v in =v en =5v, i out =0a, v out =v ref - 30 - c note 1. stresses listed as the above ?absolute maximum ratings? may cause permanent damage to the device. these are for stress ratings. functional operation of the device at thes e or any other conditions bey ond those indicated in the operational sections of the specificati ons is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in the natural convection at t a =25 c on a low effective thermal conductivity test board (sin gle layout, 1s) of jedec 51-3 thermal measurement standard. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions.
cystech electronics corp. spec. no. : c552n5 issued date : 2010.10.26 revised date : page no. : 5/10 LM1101N5 cystek product specification typical operating characteristics power on from v in power off from v in v out =3.3v c in =c out =1 f r out =15 v out =3.3v c in =c out =1 f r out =15 turn on from en turn off from en v out =3.3v c in =c out =1 f r out =15 v out =3.3v c in =c out =1 f r out =15 load transient response line transient response v out =3.3v c in =c out =1 f v out =2.5v c in =c out =1 f v in =3.5v to 4.5v v in v out v in v out i out i out v in v out i out v in v out i out
cystech electronics corp. spec. no. : c552n5 issued date : 2010.10.26 revised date : page no. : 6/10 LM1101N5 cystek product specification
cystech electronics corp. spec. no. : c552n5 issued date : 2010.10.26 revised date : page no. : 7/10 LM1101N5 cystek product specification
cystech electronics corp. spec. no. : c552n5 issued date : 2010.10.26 revised date : page no. : 8/10 LM1101N5 cystek product specification functional description enable function lm1101 is enabled if the voltage of the en pin is greater than 1.4v. if the voltage of the en pin is less than 0.4v, the ic will be disabled. por ? power on reset to let lm1101 start to operation, input voltage must be higher than its por voltage even when en voltage is pulled higher than enable high voltage . typical por voltage is 2.0v. vout voltage adjustment the v out voltage of lm1101 can be adjusted by external volta ge divider. refer to typical application circuit, v out voltage is calculated by the following equation: over current limit function lm1101 features over current limiting function wh ich can limit its output current to 600ma. input and output capacitor selection for v in pin, 1 f or larger ceramic capacitor is required to provide byp ass path in transient current demand. v out pin is also recommended to have 1 f or larger ceramic capacitor to be stable and reduce the v out voltage dip when fast loading transient is happened. power dissipation the max power depends on some conditions, including of thermal impedance, pcb layout, airflow, and so on. the max power dissipation can be calculated by the formula as below: p d(max) =(t j(max) -t a ) / ja t j(max) is the max junction temperature; ja is the thermal impedance from junction to ambient. the thermal impedance ja of sot23-5 is package design and pcb design dependent. for recommended specification of lm1101, the max junction temperature is 125 degree c. the ja of sot23-5 is 250c/w on the standard jedec 51-3 thermal test board. the max power dissipation (at 25c ambient) can be calculated as below: p d (max at 25c) =(125c ? 25c) / (250c/w) = 0.4w
cystech electronics corp. spec. no. : c552n5 issued date : 2010.10.26 revised date : page no. : 9/10 LM1101N5 cystek product specification recommended wave soldering condition soldering time product peak temperature pb-free devices 5 +1/-1 seconds 260 +0/-5 c recommended temperature profile for ir reflow pb-free assembly profile feature sn-pb eutectic assembly average ramp-up rate 3 c/second max. 3 c/second max. (tsmax to tp) preheat 100 c 150 c ? temperature min(t s min) ? temperature max(t s max) 150 c 200 c ? time(ts min to ts max ) 60-120 seconds 60-180 seconds 183 c 60-150 seconds time maintained above: ? temperature (t l ) ? time (t l ) 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of t he package, measured on the package body surface.
cystech electronics corp. spec. no. : c552n5 issued date : 2010.10.26 revised date : page no. : 10/10 LM1101N5 cystek product specification sot-25 dimension style: pin 1: enable pin 2: ground pin 3: v in pin 4: v out pin 5: feedback marking: 5-lead sot-23-5l plastic surface mounted package cystek package code:n5 device code date code *:typical millimeters inches millimeters inches dim min. min. max. dim max. min. max. min. max. a 0.90 1.30 0.0354 0.0512 c 0.08 0.22 0.0031 0.0087 a1 0.00 0.15 0.0000 0.0059 d 2.90* 0.1142* b 2.80* 0.1102* e 0.95* 0.0374* b1 1.60* 0.0630* f - 1.45 - 0.0571 b 0.30 0.50 0.0118 0.0199 g 0.30 0.60 0.0118 0.0236 notes : 1.controlling dimension : millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing specification or packing method, please c ontact your local cystek sales office. material : ? lead :pure tin plated. ? mold compound : epoxy resin family, flammability solid burning class:ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitable for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .
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